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Itanium
compiler
ERP
instruction set
microprocessor
RISC

A member of Intel's new Merced family of processors, Itanium is a 64-bit RISC microprocessor. Based on the EPIC (Explicitly Parallel Instruction Computing) design philosophy, which states that the compiler should decide which instructions be executed together, Itanium has the highest FPU power available.

In 64-bit mode, Itanium is able to calculate two bundles of a maximum of three instructions at a time. In 32-bit mode, it is much slower. Decoders must first translate 32-bit instruction sets into 64-bit instruction sets, which results in extra-clock cycle use.

Itanium's primary use is driving large applications that require more than 4 GB of memory, such as databases, ERP, and future Internet applications.



For internet.com pages about Itanium, . Also, check out the following links!


More Information

Outstanding Page Inside Intel's Merced: A Strategic Planning Discussion
In this July 1999 Executive White Paper, Aberdeen provides a general overview of Intel's IA-64 program and a detailed discussion of Merced.

Outstanding Page Itanium v. K8
HardwareCental compares and contrasts Intel's and AMD's new 64-bit microprocessors.

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